evaluates: max1121?ax1124 max1124 evaluation kit ________________________________________________________________ maxim integrated products 1 19-3098; rev 0; 12/03 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. general description the max1124 evaluation kit (ev kit) is a fully assembled and tested circuit board that contains all the compo- nents for evaluating the max1121 (8-bit, 250msps), max1122 (10-bit, 170msps), max1123 (10-bit, 210msps), and max1124 (10-bit, 250msps) analog-to- digital converters (adcs). the max1121?ax1124 accept differential analog input signals; however, the ev kit generates these signals from a user-provided single-ended signal source. the digital output pro- duced by the adcs can be easily captured with a user- provided high-speed logic analyzer or data-acquisition system. the ev kit operates from 1.8v and 3.3v power supplies. it includes circuitry that generates a differen- tial clock signal from a user-provided ac signal. the ev kit comes with the max1124 installed. contact the fac- tory for free samples of the pin-compatible max1121/ max1122/max1123 to evaluate these parts. features up to 250msps sampling rate with the max1124 low voltage and power operation fully differential signal input configuration on-board differential output drivers optional on-board secondary transformer fully assembled and tested also evaluates the max1121 (8-bit), max1122 (10-bit), and max1123 (10-bit) ordering information part temp range ic package MAX1124EVKIT 0 c to +70 c 68 qfn note: to evaluate the max1121/max1122/max1123, request a max1121egk, max1122egk, or max1123egk free sample with the max1124 ev kit. component list designation qty description c1 c11, c13 c16, c18, c19, c20, c36 c39 22 0.1f 20%, 10v x5r ceramic capacitors (0402) tdk c1005x5r1a104m c12, c17 0 not installed (0402) c21 c24 4 0.22f 20%, 6.3v x5r ceramic capacitors (0402) tdk c1005x5r0j224m c25, c26 2 not installed (0603) c27, c28, c40 3 47f 20%, 10v tantalum capacitors (c-case) avx tajc476m010 designation qty description c29, c30, c31, c41 4 10f 20%, 6.3v x5r ceramic capacitors (0805) tdk c2012x5r0j106m c32, c33, c34, c42 4 1.0f 20%, 10v x5r ceramic capacitors (0603) tdk c1608x5r1a105m c35 1 0.01f 20%, 25v x7r ceramic capacitor (0402) tdk c1005x7r1e103m j1, j2, j3 3 sma pc-mount connectors j4 j7 4 dual-row, 40-pin headers part selection table part resolution speed (msps) max1121egk 8 250 max1122egk 10 170 max1123egk 10 210 max1124egk 10 250
evaluates: max1121?ax1124 max1124 evaluation kit 2 _______________________________________________________________________________________ quick start recommended equipment dc power supplies: analog (vcc) 1.8v, 300ma clock (vclk) 3.3v, 150ma buffers (vpecl) 3.3v, 350ma signal generator with low phase noise and low jit- ter for clock input (e.g., hp8662a, hp8644b) signal generator for analog signal input (e.g., hp8662a, hp8644b) logic analyzer or data-acquisition system (e.g., hp16500c, tla621) digital voltmeter procedure the max1124 ev kit is a fully assembled and tested sur- face-mount board. follow the steps below for board oper- ation. do not turn on power supplies or enable signal generators until all connections are completed: 1) verify that shunts are installed in the following locations: ju3 (2-3) two s complement output ju4 (1-2) divide-by-two disabled ju5 (2-3) internal reference enabled 2) connect the clock signal generator to the sma con- nector labeled j2. 3) connect the analog input signal generator to the sma connector labeled j3. 4) connect the logic analyzer to either headers j4/j5 component list (continued) component suppliers designation qty description ju1 0 not installed ju3, ju4, ju5 3 jumper, 3-pin headers r1, r2, r3 3 49.9 ? 1% resistors (0603) r4, r5 2 150 ? 5% resistors (0603) r6 r9 0 not installed (0603) r10 r15, r42, r43 0 not installed (0603) r16, r17 2 10 ? 1% resistors (0603) r18 r24, r28 r32, r34, r35 14 100 ? 1% resistors (0603) r25, r26, r27, r33 4 100 ? 5% resistors (0603) r36, r37 2 510 ? 5% resistors (0603) r38, r39, r41, r44 r68 28 510 ? 5% resistors (0402) supplier phone fax website avx 843-946-0238 843-626-3123 www.avxcorp.com fairchild 888-522-5372 www.fairchildsemi.com mini-circuits 718-934-4500 718-332-4661 www.minicircuits.com tdk 847-803-6100 847-390-4405 www.component.tdk.com designation qty description r40 1 not installed t1, t2 2 1:1 800mhz rf transformers mini-circuits adt1-1wt tp1, tp2 2 test points (black) u1 1 maxim max1124egk (qfn-68) u2 1 3.3v differential receiver (so-8) fairchild 100lvel16m on semiconductor mc100lvel16d u3 u6 4 3.3v ecl quad differential receivers (so-20) on semiconductor mc100lvel17dw y1 0 not installed none 3 shunts none 1 max1124 pc board note: please indicate that you are using the max1124 when contacting these component suppliers.
(lvds-compatible signals) or j6/j7 (lvpecl-com- patible signals). see the output bit locations sec- tion for header connections. 5) connect a 1.8v, 300ma power supply to vcc. connect the ground terminal of this supply to gnd. 6) connect a 3.3v, 150ma power supply to vclk. connect the ground terminal of this supply to gnd. 7) connect a 3.3v, 350ma power supply to vpecl. connect the ground terminal of this supply to gnd. 8) turn on all of the power supplies. 9) enable the signal generators. set the clock signal generator to output a 250mhz signal with an ampli- tude of 2.4v p-p . set the analog input signal genera- tors to output the desired frequency with an ampli- tude 2v p-p . the signal generators should be phase-locked. 10) enable the logic analyzer. 11) collect data using the logic analyzer. detailed description the max1124 ev kit is a fully assembled and tested cir- cuit board that contains all the components necessary to evaluate the performance of the max1121 (8-bit, 250msps), max1122 (10-bit, 170msps), max1123 (10-bit, 210msps), and max1124 (10-bit, 250msps) lvds-out- put adcs. the ev kit comes with the max1124 installed, which can be evaluated with a maximum clock frequen- cy (f clk ) of 250mhz. the max1124 accepts differential input signals; however, an on-board transformer (t2) converts a readily available single-ended source output to the required differential signal. output level translators (u3 u6) buffer and convert the lvds output signals of the max1124 to higher-voltage lvpecl signals, which can be captured by a wide vari- ety of logic analyzers. the lvds outputs are accessed at headers j4 and j5. the lvpecl outputs are accessed at headers j6 and j7. the ev kit is designed as a four-layer pc board to opti- mize the performance of the max1124. separate ana- log, clock, and buffer power planes minimize noise- coupling between analog and digital signals. for ana- log and clock inputs, 50 ? coplanar transmission lines are used. for all digital lvds outputs, 100 ? differential coplanar transmission lines are used. all lvds differen- tial outputs are properly terminated with 100 ? termina- tion resistors between true and complementary digital outputs. the trace lengths of the 100 ? differential lvds lines are matched to within a few thousandths of an inch to minimize layout-dependent delays. power supplies the max1124 ev kit requires separate analog, clock, and buffer power supplies for best performance. a 1.8v power supply is used to power the analog and digital portion of the max1124. the on-board clock circuitry is powered by a 3.3v power supply. a separate 3.3v power supply is used to power the output buffers (u3 u6) of the ev kit. clock the max1124 requires a differential clock input signal. an on-board clock-shaping circuit generates a differen- tial clock signal from an ac sine-wave signal applied to the clock-input sma connector (j2). the input signal should not exceed an amplitude of 2.6v p-p . the fre- quency of the signal should not exceed 250mhz for the max1124. the frequency of the sinusoidal input signal determines the sampling frequency (f clk ) of the adc. a differential line receiver (u2), processes the input sig- nal to generate the required clock signal. clock divider the max1124 features an internal divide-by-two clock divider. use jumper ju4 to enable/disable this feature. see table 1 for shunt positions. input signal the max1124 accepts differential analog input signals. the max1124 ev kit only requires a single-ended ana- log input signal with an amplitude 2v p-p provided by the user. an on-board transformer takes the single- ended analog input and generates a differential analog signal at the adcs differential input pins. evaluates: max1121?ax1124 max1124 evaluation kit _______________________________________________________________________________________ 3 table 1. clock divider shunt settings (ju4) shunt position max1124 clkdiv pin description 1-2* vcc clock signal divided by 1 2-3 gnd clock signal divided by 2 * default configuration: ju4 (1-2).
evaluates: max1121?ax1124 optional secondary input transformer using the optional on-board secondary transformer can reduce common-mode signal levels and marginally improve performance of the max1124. to use this transformer, follow the directions below: 1) cut the trace at r43. 2) install 0 ? resistors at r10 and r12. 3) remove c14. 4) connect the analog signal source to j1 instead of j3. reference voltage there are two methods to set the full-scale range of the max1124. the max1124 ev kit can be configured to use the max1124 s internal reference, or a stable, low- noise external reference can be applied to the refio pad. jumper ju5 controls which reference source is used. see table 2 for shunt settings. output signal the max1124 features a single,10-bit, parallel, lvds- compatible, digital output bus. the digital outputs also feature a clock bit (clk) for data synchronization, and a data overrange bit. see the output bit locations sec- tion for header connections. output format the digital output coding can be chosen to be either in two s complement or straight offset binary format by configuring jumper ju3. see table 3 for shunt settings. output bit locations the digital outputs of the adc are connected to two 40- pin headers (j4 and j5). pc board trace lengths are matched to minimize output skew and improve perfor- mance of the device. in addition, four drivers (u3 u6) buffer and level-translate the adc s digital outputs to lvpecl-compatible signals. the drivers increase the differential voltage swing, and are able to drive large capacitive loads, which may be present at the logic analyzer connection. the outputs of the buffers are connected to two 40-pin headers (j6 and j7). see table 4 for header j4 j7 bit locations. max1124 evaluation kit 4 _______________________________________________________________________________________ table 2. reference shunt settings (ju5) shunt position description 1-2 internal reference disabled; apply a stable reference voltage at the refio pad 2-3* internal reference enabled * default configuration: ju5 (2-3). table 3. output format shunt settings (ju3) shunt position max1124 t /b pin description 1-2 vcc digital output in straight offset binary 2-3* gnd digital output in two's complement * default configuration: ju3 (2-3). table 4. output bit locations (max1122/max1123/max1124) (ju3) bit unbuffered (lvds) buffered (lvpecl) description p j6-10 j4-10 d9 n j6-9 j4-9 msb p j6-16 j4-16 d8 n j6-15 j4-15 p j6-22 j4-22 d7 n j6-21 j4-21 p j6-28 j4-28 d6 n j6-27 j4-27 p j6-34 j4-34 d5 n j6-33 j4-33 p j6-40 j4-40 d4 n j6-39 j4-39 p j7-8 j5-8 d3 n j7-7 j5-7 p j7-14 j5-14 d2 n j7-13 j5-13 p j7-20 j5-20 d1 n j7-19 j5-19 data bits p j7-26 j5-26 d0 n j7-25 j5-25 lsb p j6-4 j4-4 or n j6-3 j4-3 overrange bit p j7-2 j5-2 dco n j7-1 j5-1 clock output signal * default configuration: ju3 (2-3).
evaluating the max1121/max1122/max1123 the max1124 ev kit is also capable of evaluating the max1121/max1122/max1123. to evaluate the max1121, max1122, or max1123, replace the max1124 with the desired ic. when evaluating the 8-bit max1121, do not connect the logic analyzer to the header pins marked d0 and d1. see table 5 for output bit locations of headers j4 j7. evaluates: max1121?ax1124 max1124 evaluation kit _______________________________________________________________________________________ 5 table 5. output bit locations (max1121) bit unbuffered (lvds) buffered (lvpecl) description p j6-10 j4-10 d7 n j6-9 j4-9 msb p j6-16 j4-16 d6 n j6-15 j4-15 p j6-22 j4-22 d5 n j6-21 j4-21 p j6-28 j4-28 d4 n j6-27 j4-27 p j6-34 j4-34 d3 n j6-33 j4-33 p j6-40 j4-40 d2 n j6-39 j4-39 p j7-8 j5-8 d1 n j7-7 j5-7 data bits p j7-14 j5-14 d0 n j7-13 j5-13 lsb p j6-4 j4-4 or n j6-3 j4-3 overrange bit p j7-2 j5-2 dco n j7-1 j5-1 clock output signal
evaluates: max1121?ax1124 max1124 evaluation kit 6 _______________________________________________________________________________________ v cc c1 0.1 f c2 0.1 f c22 0.22 f c23 0.22 f c7 0.1 f c24 0.22 f c8 0.1 f v cc c21 0.22 f c3 0.1 f c4 0.1 f c5 0.1 f v cc av cc 1 6 11 12 14 20 25 62 63 65 27 28 41 44 60 13 av cc av cc av cc av cc av cc av cc av cc av cc av cc av cc ov cc ov cc ov cc ov cc ov cc 59 58 orp orn orp orn r18 100 ? 1% 5 2 16 agnd refadj 4 3 r40 open r42 short refio v cc c20 0.1 f 17 68 ju3 v cc clkn clkp vclk r15 open r14 open 4 6 1 y1 open 2 n.c. oe vclk ju1 1 2 3 out v cc vclk vclk c18 0.1 f c35 0.01 f c19 0.1 f c16 0.1 f r17 10 ? 1% c26 short c11 0.1 f clkp inn inp clkn 23 22 9 8 c17 open c12 open c25 short r11 open r10 open r43 short t2 3 5 1 6 2 4 r13 open r7 open r6 open c9 0.1 f r1 49.9 ? 1% j1 1 5 3 6 2 4 r3 49.9 ? 1% r2 49.9 ? 1% r37 510 ? r36 510 ? 2 d d v bb v ee q q n.c. v cc 18 7 6 r4 150 ? c15 0.1 f vclk clkp clkn r5 150 ? u2 mc100lvel16 3 c14 0.1 f c13 0.1 f j3 j2 r12 open c10 0.1 f tp1 r8 open r9 open r16 10 ? 1% out 5 r27 100 ? r26 100 ? r33 100 ? r25 100 ? v cc 1 2 3 ju4 1 2 3 ju5 1 2 3 refio clkdiv t/b tp2 agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd ognd ognd ognd 7 15 18 19 21 24 64 66 67 26 45 61 10 max1124 u1 57 56 d9p d9n d9p d9n d8p r19 100 ? 1% 55 54 d8p d8n d8n d7p r20 100 ? 1% 53 52 d7p d7n d7n r21 100 ? 1% d6p 51 50 d6p d6n d6n r22 100 ? 1% d5p 49 48 d5p d5n d5n r23 100 ? 1% d4p 47 46 d4p d4n d4n r24 100 ? 1% dclkp 43 42 dcop dcon dclkn r28 100 ? 1% d3p 40 39 d3p d3n d3n r29 100 ? 1% d2p 38 37 d2p d2n d2n r30 100 ? 1% d1p 36 35 d1p d1n d1n r31 100 ? 1% d0p 34 33 d0p d0n d0n r32 100 ? 1% n.c. 32 31 nc1 nc2 n.c. r34 100 ? 1% n.c. 30 29 nc3 nc4 n.c. r35 100 ? 1% orp j4 4 j4 j4? j4? j4? j4? j4? j4?2 j4?4 j4?3 j4?8 j4?0 j4?9 j4?4 j4?6 j4?5 j4?0 j4?2 j4?1 j4?6 j4?8 j4?7 orn j4? d9p j4?0 d9n j4? d8p j4?6 d8n j4?5 j4? j4?1 d7p j4?2 d7n j4?1 j4?7 d6p j4?8 d6n j4?7 j4?3 d5p j4?4 d5n j4?3 j4?9 d4p j4?0 d4n j4?9 j4?5 dcop j5? j5 j5? j5? j5? j5? j5?0 j5?2 j5?15 j5?6 j5?8 j5?1 j5?2 j5?4 j5?7 j5?8 j5?0 j5?3 j5?4 j5?6 j5?9 j5?0 dcon j5? d3p j5? d3n j5? d2p j5?4 d2n j5?3 j5? j5?1 d1p j5?0 d1n j5?9 j5?7 d0p j5?6 d0n j5?5 j5?3 nc1 j5?2 nc2 j5?1 j5?9 nc3 j5?8 nc4 j5?7 j5?5 c6 0.1 f t1 4 5 3 gnd figure 1. max1124 ev kit schematic (sheet 1 of 3)
evaluates: max1121?ax1124 max1124 evaluation kit _______________________________________________________________________________________ 7 vpecl c36 0.1 f 120 v cc v cc orp orn 2 3 do do d9p d9n 4 5 d1 d1 d8p d8n 6 7 d2 d2 d7p d7n 8 9 d3 d3 q0 borp born r41 510 ? r44 510 ? q0 19 18 q1 bd9p bd9n r45 510 ? r46 510 ? q1 17 16 q2 bd8p bd8n r47 510 ? r48 510 ? q2 15 14 q3 bd7p bd7n r49 510 ? r50 510 ? q3 13 12 v ee v bb 10 11 u3 vpecl c38 0.1 f 120 v cc v cc d6p d6n 2 3 do do d5p d5n 4 5 d1 d1 d4p d4n 6 7 d2 d2 8 9 d3 d3 q0 bd6p bd6n r38 510 ? r39 510 ? q0 19 18 q1 bd5p bd5n r51 510 ? r52 510 ? q1 17 16 q2 bd4p bd4n r53 510 ? r54 510 ? q2 15 14 q3 q3 13 12 v ee v bb 10 11 u4 vpecl c37 0.1 f 120 v cc v cc dcop dcon 2 3 do do d3p d3n 4 5 d1 d1 d2p d2n 6 7 d2 d2 d1p d1n 8 9 d3 d3 q0 bdcop bdcon r57 510 ? r58 510 ? q0 19 18 q1 bd3p bd3n r59 510 ? r60 510 ? q1 17 16 q2 bd2p bd2n r61 510 ? r62 510 ? q2 15 14 q3 bd1p bd1n r63 510 ? r64 510 ? q3 13 12 v ee v bb 10 11 u5 vpecl c39 0.1 f 120 v cc v cc dop don 2 3 do do nc1 nc2 4 5 d1 d1 nc3 nc4 6 7 d2 d2 8 9 d3 d3 q0 bdop bdon r55 510 ? r56 510 ? q0 19 18 q1 bnc1 bnc2 r65 510 ? r66 510 ? q1 17 16 q2 bnc3 bnc4 r67 510 ? r68 510 ? q2 15 14 q3 q3 13 12 v ee v bb 10 11 u6 bdcop j7 2 bdcon j7 1 j7 5 bd3p j7 8 bd3n j7 7 bd2p j7 14 bd2n j7 13 j7 17 bd1p j7 20 bd1n j7 19 j7 23 bd0p j7 26 bd0n j7 25 j7 29 bnc1 j7 32 bnc2 j7 31 j7 35 bnc3 j7 38 bnc4 j7 37 j7 11 j7 3 j7 4 j7 6 j7 9 j7 10 j7 15 j7 16 j7 18 j7 21 j7 22 j7 24 j7 27 j7 28 j7 30 j7 33 j7 34 j7 36 j7 39 j7 40 j7 12 j7 b0rp j6 4 b0rn j6 3 j6 1 bd9p j6 10 bd9n j6 9 bd8p j6 16 bd8n j6 15 j6 17 bd7p j6 22 bd7n j6 21 j6 23 bd6p j6 28 bd6n j6 27 j6 29 bd5p j6 34 bd5n j6 33 j6 35 bd4p j6 40 bd4n j6 39 j6 11 j6 2 j6 5 j6 6 j6 8 j6 7 j6 14 j6 13 j6 18 j6 20 j6 19 j6 24 j6 26 j6 25 j6 30 j6 32 j6 31 j6 36 j6 38 j6 37 j6 12 j6 mc100lvel17 mc100lvel17 mc100lvel17 mc100lvel17 figure 1. max1124 ev kit schematic (sheet 2 of 3)
figure 2. component placement guide?omponent side evaluates: max1121?ax1124 max1124 evaluation kit 8 _______________________________________________________________________________________ c27 47 f 10v c29 10 f vclk vclk gnd c32 1.0 f c40 47 f 10v c41 10 f vpecl vpecl gnd c42 1.0 f c28 47 f 10v c30 10 f c31 10 f c34 1.0 f v cc v cc gnd c33 1.0 f figure 1. max1124 ev kit schematic (sheet 3 of 3)
evaluates: max1121?ax1124 max1124 evaluation kit _______________________________________________________________________________________ 9 figure 3. pc board layout?omponent side figure 4. pc board layout (inner layer 2)?round planes
maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 10 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2003 maxim integrated products printed usa is a registered trademark of maxim integrated products. evaluates: max1121?ax1124 max1124 evaluation kit figure 6. pc board layout?older side figure 5. pc board layout (inner layer 3)?ower planes
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